The present invention relates to a nonvolatile semiconductor memory in which a shielded bit line sensing scheme is used in data read.
Hitherto, in a nonvolatile semiconductor memory, for example, a NAND flash memory EEPROM structured as shown in FIG. 1, data read is conducted for each page (a memory cell group connected to one word line).
A data read operation will now be described in brief. After all of bit lines BL0, BL1, . . . , BLi are precharged to 2.5 V. Then, all of the bit lines BL0, BL1, . . . , BLi are brought to a floating state. In selected block BLKj, select gates SGS and SGD of select transistors at both ends of NAND cell units and non-selected word lines (control gates) CG0, CG1, CG3 to CG15 are set to VCGH (=3.5 V). Moreover, a selected word line (a control gate) CG2 is set to the ground potential (=0 V). In non-selected blocks, select gates SGS and SGD of the select transistors at both ends of the NAND cell units are set to the ground potential (=0 V).
The threshold voltage of a memory cell for storing, for example, data "1" is set to a level lower than 0 V. On the other hand, the threshold voltage of the memory cell for storing, for example, data "0" is set to a level higher than 0 V and lower than 3.5 V. A source line SL is set to the ground potential (=0 V).
In the selected block BLkj, the select transistors at the NAND cell units are turned on at this time. Also the memory cells which are connected to the non-selected word lines CG0, CG1, CG3 to CG15 are turned on regardless of the value of data ("1" or Therefore, the potentials of the bit lines BL0, BL1, . . . , BLi are determined in accordance with data in each of the memory cells connected to the selected word line CG2. For example, if data in memory cell M0 is "1", the threshold voltage of the memory cell M0 is lower than 0 V. Therefore, the memory cell M0 is turned on so that the electric charge of the bit line BL0 is discharged to a source line SL (=0 V). For example, if data in memory cell M1 is "0", the threshold voltage of the memory cell M1 is higher than 0 V. Therefore, the memory cell M1 is turned off. Thus, the bit line BL1 maintains the precharge potential.
Thus, the potential of each of the bit lines BL0, BL1, . . . , BLi is changed from the precharge potential to the ground potential (=0 V) when data in the select cells is "1". When data in the select cells is "0", the precharge potential is maintained.
The potential (data) of the bit lines BL0, BL1, . . . , BLi are amplified and latched by a latch circuit having a function of a sense amplifier. Thus, the data read operation is completed.
The nonvolatile semiconductor memory for performing a data read operation for each page has the following defects.
If the memory cells are fixed due to increasing memory capacity, a parasitic capacity between two adjacent bit lines becomes larger than a parasitic capacity between the bit line and the ground point (for example, a semiconductor substrate). In the case, for example, discharge of electricity from the bit lines BLi-1 and BLi+1 on both sides of the bit line BLi which must maintain the precharge potential sometimes causes the potential of the bit line BLi to also be lowered correspondingly to the discharge of the bit lines BLi-1 and BLi+1. Thus, a read error sometimes occurs.
To prevent such a read error, a data read scheme, that is, a shielded bit line sensing scheme is employed, in which data read in memory cell groups corresponding to one page connected to one word line is performed by two kinds of read operations consisting of an operation for reading data in memory cells connected to even-numbered bit lines and an operation for reading data in memory cells connected to odd-numbered bit lines.
The method will now be described. A first read operation is performed for example such that, while the odd-numbered bit lines BL1, BL3, . . . , are fixed to the ground potential GND, data in the memory cells are output to only the even-numbered bit lines BL0, BL2, . . . , and then data is latched by the latch circuit. A second read operation is performed for example such that, while even-numbered bit lines BL0, BL2, . . . are fixed to the ground potential GND, data is output to only the odd-numbered bit lines BL1, BL3, . . . , and the data is latched by the latch circuit.
With the shielded bit line sensing scheme, since the bit lines BLi-1 and BLi+1 on both sides of the bit line BLi which receives data are fixed to the ground potential GND, change in the potential of the bit line BLi can be prevented which is caused from change in the potential of the bit lines BLi-1 and BLi+1.
FIG. 2 is a diagram showing a main portion of the structure of a NAND flash EEPROM to which the shielded bit line sensing scheme is applied.
A memory cell array 11 comprises a plurality of NAND cell units 12 arranged in an array configuration. Each of the NAND cell units 12 is structured with a NAND column composed of a plurality of memory cells connected in series and two select transistors connected to both ends of the NAND column (see FIG. 1).
In each of blocks BLK0, BLK1, BLK2, . . . , of the memory cell array 11, is arranged a line group 14 including select gates SGS and SGD and word lines (control gates) CG0 to CG15 of select transistors extending in a row direction. A row decoder 13 selects one block in response to a block address signal.
A select gate driver 15 applies VCGH (=3.5 V) to the select gates SGS and SGD of the select transistors at both ends of the NAND cell units 12 in the selected blocks. Moreover, the row decoder 13 applies the ground potential to the select gate SGS and SGD of the select transistors at both ends of the NAND cell units 12 in the non-selected blocks. The row decoder 13 applies VCGH (=3.5 V) to the non-selected word lines and applies the ground potential to the selected word lines.
A source line SL is connected to ends of the NAND cell units 12. A source is shared by the NAND cell units (NAND cell units in one block) 12 in the row direction, and is connected to the source line SL. The source line SL is common to all of the NAND cell units 12 in the memory cell array 11, and is applied with the ground potential.
A predetermined one of bit lines BLi-1, BLi, BLi+1, BLi+2, . . . , is connected to the other ends of the NAND cell units 12 in the column direction. One end of each of the bit lines BLi-1, BLi, BLi+1, BLi+2, . . . , is connected to a VDD/GND supply circuit 18 through a switch circuit 17 for switching the precharge potential and the shield potential.
For example, if the bit lines BLi-1, BLi+1, . . . , are shield bit lines and the bit lines BLi, BLi+2, . . . , are selected bit lines, signal BLCDO is set to VDD (power source potential=2.5 V), the VDD (power source potential=2.5 V) is supplied from the VDD/GND supply circuit 18 to the bit lines BLi, BLi+2, . . . , to precharge the bit lines BLi, BLi+2, . . . , to VDD, and then signal BLCDO is set to 0 V. Then, the signal BLCDE is made to be VDD (power source potential=2.5 V), and the ground potential GND is supplied from the VDD/GND supply circuit 18 to the bit lines BLi-1, BLi+1, . . . , to fix the bit lines BLi-1, BLi+1, . . . , to the ground potential GND.
The reason why the potential of the shield bit line is made to be the ground potential (=0 V) lies in that the potential of the source line SL has been set to be 0 V. If the potential of the shield bit line is made to be the power source potential VDD, a short is caused between the shield bit line (the power source potential), which and the source line (the ground potential) are short-circuited through the NAND column when all of the transistors of the NAND cells in the selected blocks connected to the shield bit line are turned on. In this case, a large electric current flows, causing power loss.
The other end of each of the bit lines BLi-1, BLi, BLi+1, BLi+2, . . . , is connected to a latch circuit 20 having a function of a sense amplifier through the switch circuit 19. For example, the bit lines BLi-1, BLi+1, . . . , are made to be shield bit lines and the bit lines BLi, BLi+2, . . . , are made to be selected bit lines, signal BLCUE is made to be the ground potential GND and signal BLCUO is made to be the power source potential VDD, so that the potentials (data) of the shield bit lines BLi, BLi+2, . . . , can be applied to the latch circuit 20 having the function of the sense amplifier.
A column decoder 21 selects one column in response to the column address signal. Data in the latch circuit 20 in the selected column is supplied to an I/O buffer 23 through a column select circuit 22.
If one chip includes, for example, n memory cell arrays, n I/O buffers and n I/O pads, an output of n-bit data is simultaneously output to the outside.
A conventional device structure of the NAND flash EEPROM to which the shielded bit line sensing scheme is applied will now be described.
FIG. 3 shows a layout pattern of a source contact section of the memory cell array 11 shown in FIG. 2. FIG. 4 shows a pattern of a device isolation film of the memory cell array 11 shown in FIG. 2. FIG. 5 is a cross-sectional view taken along line V--V shown in FIG. 3. FIG. 6 is a cross-sectional view taken along line VI--VI shown in FIG. 3.
A device isolation film 31 of an STI (Shallow Trench Isolation) structure formed on a semiconductor substrate 30. The device isolation film 31 electrically isolates two adjacent NAND cell units from each other. The semiconductor substrate includes a plurality of N-type diffusion layers 32 and 32a formed therein.
The N-type diffusion layer 32a serves as a source of the NAND cell unit, the N-type diffusion layer 32a being commonly used by a plurality of NAND cell units in the row direction. Floating gates 33, . . . , and control gates CG15, CG14, . . . , of the memory cell are formed on channels between the N-type diffusion layers 32. Select gates SGS of the select transistors are formed on the channels between the N-type diffusion layers 32 and 32a.
An interlayer insulating film 34 is formed to cover the NAND cell units comprising the memory cell and the select transistors. A source line SL which is connected to the N-type diffusion layer 32a is formed on the interlayer insulating film 34. An interlayer insulating film 35 for covering the source line SL is formed on the interlayer insulating film 34. Bit lines BLi-1, BLi, BLi+1, BLi+2 which are connected to the drains of the NAND cell units are formed on the interlayer insulating film 35.
The shielded bit line sensing scheme using the NAND flash EEPROM shown in FIG. 2 will now be described.
Initially, a first data read operation is performed.
The signals BLCUE and BLCUO are made to be the ground potential, and all of the transistors in the switch circuit 19 are turned off. When the bit lines BLi-1, BLi+1, . . . , are made to be the shield bit lines, and the bit lines BLi, BLi+2, . . . , are made to be selected bit lines, the signal BLCDO is set to VDD (power source potential=2.5 V) and the signal BLCDE is set to the ground potential GND. Then, VDD (power source potential=2.5 V) is supplied from the VDD/GND supply circuit 18 to the bit lines BLi, BLi+2, . . . , so that the bit lines BLi, BLi+2, . . . , are precharged to VDD. Thereafter, when the signal BLCDO is set to the ground potential GND, the bit lines BLi, BLi+2, . . . , are brought to a floating state.
Then, the signal BLCDE is set to VDD (power source potential=2.5 V) and the ground potential GND is supplied from the VDD/GND supply circuit 18 to the bit lines BLi-1, BLi+1, . . . so that the bit lines Bli-1, BLi+1, . . . , are made to be the ground potential GND. If the signal BLCDE maintains the power source potential VDD, the shield bit lines BLi-1, BLi+1, . . . , can be fixed to the ground potential GND.
Then, the row decoder 13 selects one block and one word line (a row) in response to a block address signal and a row address signal. The select gate driver 15 applies VCGH (=3.5 V) to the select gates SGS and SGD of the select transistors at both ends of the NAND cell units in the selected blocks, while applying the ground potential to the select gates SGS and SGD of the select transistors at both ends of the NAND cell units in the non-selected blocks. The control gate driver 16 applies VCGH (=3.5 V) to the non-selected word lines while applying the ground potential to the selected word lines.
For example, the selected bit lines BLi, BLi+2, . . . , maintain the precharge potential when data in the memory cells connected to the selected word lines is "0" (when the threshold voltage is higher than 0 V), while, when data in the memory cells connected to the selected word lines is "1" (when the threshold voltage is lower than 0 V), they discharge to be made to be the ground potential.
Thereafter, the signal BLCUO becomes the power source potential and data output to the selected bit lines BLi, BLi+2 is introduced to the latch circuit 20 having the function of the sense amplifier. Data in the latch circuit 20 having the function of the sense amplifier is supplied to the I/O buffer 23 through the column select circuit 22, and then transmitted to the outside of the chip.
Then, the selected bit lines and the shield bit lines are switched, that is, the bit lines BLi, BLi+2, . . . , are changed to the shield bit lines and the bit lines BLi-1, BLi+1, . . . , are changed to the selected bit lines. Then, a second data read operation is performed.
Both of the signals BLCUE and BLCUO are set to the ground potential so that all of the transistors in the switch circuit 19 are turned off. When the bit lines BLi, BLi+2, . . . , are made to be the shield bit lines, and the bit lines BLi-1, BLi+1, . . . , are made to be the selected bit lines, the signal BLCDE is set to VDD (power source potential=2.5 V), the signal BLCDO is set to the ground potential GND, and VDD (power source potential=2.5 V) is supplied from the VDD/GND supply circuit 18 to the bit lines BLi-1, BLi+1, . . . , so that the bit lines BLi-1, BLi+1, . . . , are precharged. Thereafter, when the signal BLCDE is set to the ground potential GND, the bit lines BLi-1, BLi+1, . . . , are brought to the floating state.
Then, the signal BLCDO is made to be VDD (power source potential=2.5 V), the ground potential GND is supplied from VDD/GND supply circuit 18 to the bit lines BLi, BLi+2, . . . , and the bit lines BLi, BLi+2, . . . , are changed to the ground potential GND. If the BLCDO maintains the power source potential VDD, the shield bit lines BLi, BLi+2, . . . , can be fixed to the ground potential GND.
Then, one block and one word line (a row) is selected by the row decoder 13 in response to the block address signal and the row address signal. The select gate driver 15 applies VCGH (=3.5 V) to the select gates SGS and SGD of the select transistors at both ends of the NAND cell units in the selected block, while supplying the ground potential GND to the select gates SGS and SGD of the select transistors at both ends of the NAND cell units in the non-selected blocks. The control gate driver 16 applies VCGH (=3.5 V) to the non-selected word line and applies the ground potential GND to the selected word lines.
For example, the selected bit lines BLi-1, BLi+1, . . . , maintain the precharge potential when data in the memory cells connected to the selected word lines is "0" (when the threshold voltage is higher than 0 V), while when data in the memory cells connected to the selected word lines is "1" (when the threshold voltage is lower than 0 V), they discharge to be changed to the ground potential.
Thereafter, the signal BLCUE is made to be the power source potential, and data output to the selected bit lines BLi-1, BLi+1, . . . is supplied to the latch circuit 20 having the function of the sense amplifier. Data from the latch circuit 20 having the function of the sense amplifier is supplied to the I/O buffer 23 through the column select circuit 22, and then transmitted to the outside of the chip.
According to the above-mentioned shielded bit line sensing scheme, the bit lines on both sides of the selected bit line are fixed to the ground potential, so that the change of the potential of the selected bit line caused from change in the potential of the adjacent bit line can be prevented.
However, the bit lines (the shield bit lines) on both sides of the selected bit line are fixed to the ground potential, so that, when the selected bit line is precharged to the power source potential VDD, there arises a problem in that the capacity between the selected bit line and the shield bit line undesirably causes precharge time to be prolonged.
As shown in FIGS. 7 and 8, the stress of the potential difference of 3.5 V (VCGH-0 V) is imposed between the channels of the memory cells MC, which are connected to the shield bit line and non-selected word lines (the control gates) CG0, CG1, CG3 to CG15, and the control gate.
The stress relationship (the control gate is a high potential and the channel is a low potential) is the same as the stress relationship in an operation for writing "0", that is, in an operation for implanting electrons into the floating gate. If the above-mentioned stress is repeatedly imposed on the memory cell, a so-called soft program occurs. If the worst happens, a memory cell in an erased state (in a state in which "1" has been written, that is, a depletion type) is changed to a write state (in a state in which "0" has been written, that is, an enhancement type).